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19-0378; Rev 3; 9/96
Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs
_______________General Description
The MAX520/MAX521 are quad/octal, 8-bit voltage-output digital-to-analog converters (DACs) with simple 2-wire serial interfaces that allow communication between multiple devices. They operate from a single +5V supply and their reference input range includes both supply rails. The MAX521 includes rail-to-rail output buffer amplifiers for reduced system size and component count when driving loads. The MAX520's unbuffered voltage outputs reduce the device's total supply current to 4A and provide increased accuracy at low output currents. The MAX520/MAX521 feature a serial interface and internal software protocol, allowing communication at data rates up to 400kbps. The interface, combined with the doublebuffered input configuration, allows the DAC registers to be updated individually or simultaneously. In addition, the devices can be put into a low-power shutdown mode that reduces supply current to 4A. Power-on reset ensures the DAC outputs are at 0V when power is initially applied. The MAX520 is available in 16-pin DIP and wide SO packages, as well as a space-saving 20-pin SSOP. The MAX521 comes in 20-pin DIP and 24-pin SO packages, as well as a space-saving 24-pin SSOP.
____________________________Features
o o o o Single +5V Supply Simple 2-Wire Serial Interface I2C Compatible Outputs Swing Rail to Rail: Unbuffered Outputs (MAX520) Buffered Outputs (MAX521) 1%-Accurate Trimmed Output Resistance (MAX520A) Ultra-Low 4A Supply Current (MAX520) Individual DACs Have Separate Reference Inputs Power-On Reset Clears All Latches 4A Power-Down Mode
MAX520/MAX521
o o o o o
______________Ordering Information
PART
TEMP. RANGE 0C to +70C 0C to +70C 0C to +70C 0C to +70C
PIN-PACKAGE 16 Plastic DIP 16 Plastic DIP 16 Wide SO 16 Wide SO
TUE (LSB) 1 1 1 1
MAX520ACPE MAX520BCPE MAX520ACWE MAX520BCWE
________________________Applications
Minimum Component Analog Systems Digital Offset/Gain Adjustment Industrial Process Control Automatic Test Equipment Programmable Attenuators
Ordering Information continued at end of data sheet. MAX520 "A" grade parts include a 1%-accurate, factory-trimmed output resistance.
_______________Functional Diagrams
SDA SCL REF1 INPUT LATCH 0 1 OUTPUT LATCH 0 REF0 DAC0 OUT0
_________________Pin Configurations
TOP VIEW
MAX520
8 8-BIT SHIFT REGISTER OUT1 OUT0 1 2 16 OUT2 15 OUT3 14 REF2 ADDRESS COMPARATOR START/STOP DETECTOR
INPUT LATCH 1 1
OUTPUT LATCH 1
DAC1
OUT1
REF1 3 REF0 4 AGND 5 DGND 6 SCL 7 SDA 8
MAX520
13 REF3 12 VDD 11 AD2 10 AD1 9 AD0 AD0 AD1 AD2 DECODE 4
INPUT LATCH 2 1 INPUT LATCH 3 1
OUTPUT LATCH 2
DAC2
OUT2
OUTPUT LATCH 3
DAC3
OUT3
DIP/SO
REF2
REF3
Pin Configurations continued at end of data sheet.
Functional Diagrams continued at end of data sheet.
1
________________________________________________________________ Maxim Integrated Products
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Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs MAX520/MAX521
ABSOLUTE MAXIMUM RATINGS
VDD to DGND ...........................................................-0.3V to +6V VDD to AGND............................................................-0.3V to +6V OUT_ ..........................................................-0.3V to (VDD + 0.3V) REF_ ...........................................................-0.3V to (VDD + 0.3V) AD0, AD1, AD2...........................................-0.3V to (VDD + 0.3V) SCL, SDA to DGND ..................................................-0.3V to +6V AGND to DGND.....................................................-0.3V to +0.3V Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70C) 16-Pin Plastic DIP (derate 10.53mW/C above +70C)....842mW 20-Pin Plastic DIP (derate 11.11mW/C above +70C)....889mW 16-Pin Wide SO (derate 9.52mW/C above +70C) ......762mW 24-Pin Wide SO (derate 11.76mW/C above +70C) ....941mW 20-Pin SSOP (derate 8.00mW/C above +70C) .........640mW 24-Pin SSOP (derate 8.00mW/C above +70C) .........640mW 16-Pin CERDIP (derate 10.00mW/C above +70C)....800mW 20-Pin CERDIP (derate 11.11mW/C above +70C)....889mW Operating Temperature Ranges MAX520_C_ _/MAX521_C_ _ ..............................0C to +70C MAX520_E_ _/MAX521_E_ _ ...........................-40C to +85C MAX520_MJE/MAX521BMJP ........................-55C to +125C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 5V 10%, VREF_ = 4V, RL = (MAX520), RL = 10k (MAX521), CL = 0pF (MAX520), CL = 100pF (MAX521), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C) PARAMETER STATIC ACCURACY Resolution MAX520_ Total Unadjusted Error Differential Nonlinearity TUE DNL MAX521A MAX521B Guaranteed monotonic MAX520_ Zero-Code Error ZCE Code = 00 hex MAX521_C MAX521_E MAX521BM Zero-Code-Error Supply Rejection Zero-Code-Error Temperature Coefficient Code = 00 hex Code = 00 hex MAX520_ Full-Scale Error Code = FF hex MAX521_C MAX521_E MAX521BM Full-Scale-Error Supply Rejection Full-Scale-Error Temperature Coefficient Code = FF hex, VDD = 5V 10% 1 10 1 10 8 18 20 20 mV V/C mV 8 1 1.5 2 1.0 8 18 20 20 mV V/C mV LSB LSB Bits SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V 10%, VREF_ = 4V, RL = (MAX520), RL = 10k (MAX521), CL = 0pF (MAX520), CL = 100pF (MAX521), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C) PARAMETER REFERENCE INPUTS Input Voltage Range Input Resistance Input Current Input Capacitance RIN Code = 55 hex (Note 1) PD = 1 Code = FF hex (Note 2) (Note 3) (Note 4) 0 MAX520A MAX520B MAX521_, OUT_ = 4V, 0mA to 2.5mA Output Load Regulation MAX521_C/E, VREF_ = VDD, code = FF hex, 0A to 500A MAX521BM, VREF_ = VDD, code = FF hex, 0A to 500A Output Leakage Current DIGITAL INPUTS SCL, SDA Input High Voltage Input Low Voltage Input Current Input Hysteresis Input Capacitance DIGITAL INPUTS AD0, AD1 Input High Voltage Input Low Voltage Input Leakage DIGITAL OUTPUT SDA (Note 6) Output Low Voltage Three-State Leakage Current Three-State Output Capacitance VOL IL COUT ISINK = 3mA ISINK = 6mA VIN = 0V to VDD (Note 5) 0.4 0.6 10 10 V A pF VIH VIL IIN VIN = 0V to VDD 2.4 0.8 10 V V A VIH VIL IIN VHYST CIN 0V VIN VDD (Note 5) (Note 5) 0.05VDD 10 0.7VDD 0.3VDD 10 V V A V pF MAX521_, OUT_ = 0V to VDD, PD = 1 TA = +25C TA = TMIN to TMAX 15.8 15.6 8.4 0.25 1.5 2.0 10 A LSB 16 16 MAX520_ REF4 MAX521_ REF0-REF3 MAX520_ MAX521_ 30 120 30 -70 -60 -70 VDD 16.2 16.4 16.4 k MAX520_ MAX521_ REF4 REF0-REF3 0 8 4 16 VDD 12 6 24 10 V k A pF SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX520/MAX521
Channel-to-Channel Isolation AC Feedthrough DAC OUTPUTS Full-Scale Output Voltage Output Resistance (Note 5)
dB dB V
_______________________________________________________________________________________
3
Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs MAX520/MAX521
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V 10%, VREF_ = 4V, RL = (MAX520), RL = 10k (MAX521), CL = 0pF (MAX520), CL = 100pF (MAX521), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C) PARAMETER DYNAMIC PERFORMANCE MAX521_C Voltage Output Slew Rate Positive and negative MAX521_E MAX521BM MAX520_, to 1/2LSB, no load Output Settling Time MAX521_, to 1/2LSB, 10k and 100pF load (Note 7) Code = 00 hex, all digital inputs from 0V to VDD Code 128 to 127 SINAD VREF_ = 4Vp-p at 1kHz, VDD = 5V, code = FF hex VREF_ = 4Vp-p, 3dB bandwidth MAX521_ VDD Operating mode, out- MAX520_ put unloaded, all dig- MAX521_C ital inputs 0V or VDD MAX521_E/BM Power-down mode (PD = 1) 4.5 4 10 10 4 1.0 0.7 0.5 2 s 6 5 12 87 1 60 5.5 20 20 24 20 nV-s nV-s dB MHz VRMS V A mA A V/s SYMBOL CONDITIONS MIN TYP MAX UNITS
Digital Feedthrough Digital-Analog Glitch Impulse Signal to Noise + Distortion Ratio Multiplying Bandwidth Wideband Amplifier Noise POWER REQUIREMENTS Supply Voltage
Supply Current
IDD
Note 1: Input resistance is code dependent. The lowest input resistance occurs at code = 55 hex. Note 2: Input capacitance is code dependent. The highest input capacitance occurs at code = FF hex. Note 3: VREF_ = 4Vp-p, 10kHz. Channel-to-channel isolation is measured by setting the code of one DAC to FF hex and setting the code of all other DACs to 00 hex. Note 4: VREF_ = 4Vp-p, 10kHz, DAC code = 00 hex. Note 5: Guaranteed by design. Note 6: I2C-compatible mode. Note 7: Output settling time is measured by taking the code from 00 hex to FF hex, and from FF hex to 00 hex.
4
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Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs
TIMING CHARACTERISTICS
(VDD = 5V 10%, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER Serial Clock Frequency Bus Free Time Between a STOP and a START Condition Hold Time, (Repeated) Start Condition Low Period of the SCL Clock High Period of the SCL Clock Setup Time for a Repeated START Condition Data Hold Time Data Setup Time Rise Time of Both SDA and SCL Signals, Receiving Fall Time of Both SDA and SCL Signals, Receiving Fall Time of SDA Transmitting (Note 6) Setup Time for STOP Condition Capacitive Load for Each Bus Line Pulse Width of Spike Suppressed SYMBOL fSCL tBUF tHD, STA tLOW tHIGH tSU, STA tHD, DAT tSU, DAT tR tF tF tSU, STO Cb tSP (Notes 10, 11) 0 (Note 9) (Note 9) ISINK 6mA (Note 9) (Note 8) CONDITIONS MIN 0 1.3 0.6 1.3 0.6 0.6 0 100 20 + 0.1Cb 20 + 0.1Cb 20 + 0.1Cb 0.6 400 50 300 300 250 0.9 TYP MAX 400 UNITS kHz s s s s s s ns ns ns ns s pF ns
MAX520/MAX521
Note 8: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) in order to bridge the undefined region of SCL's falling edge. Note 9: Cb = total capacitance of one bus line in pF. tR and tf measured between 0.3VDD and 0.7VDD. Note 10: An input filter on the SDA and SCL input suppresses noise spikes less than 50ns. Note 11: Guaranteed by design.
__________________________________________Typical Operating Characteristics
(VDD = 5V, DAC outputs unloaded, TA = +25C, unless otherwise noted.)
MAX520 REFERENCE INPUT CURRENT vs. TEMPERATURE (SHUTDOWN MODE)
MAX520/521-01 MAX520/521-02
MAX520 SUPPLY CURRENT vs. TEMPERATURE
10 9 8 7 IDD (A) 6 5 4 3 2 1 0 -60 -30 0 30 60 90 120 150 TEMPERATURE (C) OPERATING MODE OR SHUTDOWN MODE 40 SHUTDOWN REFERENCE CURRENT (nA) 35 30 25 20 15 10 5 0 -60
MAX520 REFERENCE VOLTAGE INPUT FREQUENCY RESPONSE
0 RELATIVE OUTPUT (dB) -2 -4 -6 -8 -10 -12 -14 -16 -18 VDD = 5V VREF = 4Vp-p SINE WAVE CENTERED AT 2.5V
MAX520/521-03
2
VREF = 4V ONE REF INPUT DRIVEN
-30
0
30
60
90
120
150
1k
10k
100k FREQUENCY (Hz)
1M
10M
TEMPERATURE (C)
_______________________________________________________________________________________
5
Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs MAX520/MAX521
______________________________Typical Operating Characteristics (continued)
(VDD = 5V, DAC outputs unloaded, TA = +25C, unless otherwise noted.)
MAX520 POSITIVE SETTLING TIME
MAX520 NEGATIVE SETTLING TIME
OUT2 1V/div
OUT2 1V/div
1s/div OUT2 = NO LOAD, REF2 = 4V, DAC CODE = 00 HEX to FF HEX
1s/div OUT2 = NO LOAD, REF2 = 4V, DAC CODE = FF HEX to 00 HEX
MAX520 WORST-CASE 1LSB DIGITAL STEP CHANGE (CAPACITIVE LOAD < 5pF)
MAX520 WORST-CASE 1LSB DIGITAL STEP CHANGE (CAPACITIVE LOAD = 25pF)
OUT2 20mV/div AC COUPLED
OUT2 20mV/div AC COUPLED
500ns/div REF2 = 4V, DAC CODE = 7F HEX to 80 HEX
500ns/div REF2 = 4V, DAC CODE = 7F HEX to 80 HEX
6
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Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs
__________________________________________Typical Operating Characteristics
(VDD = 5V, DAC outputs unloaded, TA = +25C, unless otherwise noted.)
MAX521 SUPPLY CURRENT vs. TEMPERATURE
MAX520/521-08
MAX520/MAX521
MAX521 SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE
VDD = 5.5V ALL REF INPUTS = 0.6V ALL DIGITAL INPUTS to VDD
MAX520/521-09
MAX521 SUPPLY CURRENT vs. REFERENCE VOLTAGE
ALL REFERENCE INPUTS DRIVEN
MAX520/521-10
12 10 8 ICC (mA) 6 4
VDD = 5.5V ALL REF INPUTS = 0.6V ALL DIGITAL INPUTS to VDD ALL DAC CODES FF HEX
6 5 SHUTDOWN ICC (A) 4 3 2 1 0
10
8
ICC (mA)
6 ALL DAC CODES = FF HEX
4
ALL DAC CODES 00 HEX 2 0 -60 -20 20 60 100 140 TEMPERATURE (C) 2 ALL DAC CODES = 00 HEX
0 -60 -20 20 60 100 140 0 1 2 3 4 5 TEMPERATURE (C) REFERENCE VOLTAGE (V)
MAX521 DAC OUTPUT HIGH VOLTAGE vs. OUTPUT SOURCE CURRENT
MAX520/521-11
MAX521 DAC OUTPUT LOW VOLTAGE vs. OUTPUT SINK CURRENT
VREF = 5V DAC CODE = 00 HEX LOAD to VDD
MAX520/521-12
MAX521 REFERENCE VOLTAGE INPUT FREQUENCY RESPONSE
0 RELATIVE OUTPUT (dB) -2 -4 -6 -8 -10 -12 -14 -16 VREF = SINE WAVE CENTERED AT 2.5V 1k 10k 100k FREQUENCY (Hz) 1M 10M 4Vp-p SINE 2Vp-p SINE 1Vp-p SINE 0.5Vp-p SINE
MAX520/521-13
1.0
0.8 VDD - VOUT (V)
VREF = 5V DAC CODE = FF HEX LOAD to AGND
1.0
2
0.8
0.4
VOUT (V) VOUT = VREF x (255/256) 0 2 4 6 8 10 12 14 16
0.6
0.6
0.4
0.2
0.2
0
0 0 2 4 6 8 10 OUTPUT SINK CURRENT (mA)
-18
OUTPUT SOURCE CURRENT (mA)
MAX521 POSITIVE SETTLING TIME
MAX521 NEGATIVE SETTLING TIME
OUT1 1V/div
OUT1 1V/div
1s/div OUT1 LOADED WITH 10k II 100pF, REF1 = 4V, DAC CODE = 00 HEX to FF HEX
1s/div OUT1 LOADED WITH 10k II 100pF, REF1 = 4V, DAC CODE = FF HEX to 00 HEX
_______________________________________________________________________________________
7
Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs MAX520/MAX521
______________________________Typical Operating Characteristics (continued)
(VDD = 5V, DAC outputs unloaded, TA = +25C, unless otherwise noted.)
MAX521 WORST-CASE 1LSB DIGITAL STEP CHANGE
OUT1 20mV/div AC COUPLED
500ns/div REF1 = 5V, DAC CODE = 80 HEX to 7F HEX
CLOCK FEEDTHROUGH
REFERENCE FEEDTHROUGH AT 1kHz
A
A
B B
A = SCL, 400kHz, 5V/div B = OUT1, 5mV/div REF1 = 5V, DAC CODE = 7F HEX
A = REF1, 1V/div (4VP-P) B = OUT1, 50V/div, UNLOADED FILTER PASSBAND = 100Hz to 10kHz, DAC CODE = 00 HEX
REFERENCE FEEDTHROUGH AT 10kHz
REFERENCE FEEDTHROUGH AT 100kHz
A
A
B
B
A = REF1, 1V/div (4VP-P) B = OUT1, 50V/div, UNLOADED FILTER PASSBAND = 1kHz to 100kHz, DAC CODE = 00 HEX
A = REF1, 1V/div (4VP-P) B = OUT1, 50V/div, UNLOADED FILTER PASSBAND = 10kHz to 1MHz, DAC CODE = 00 HEX
8
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Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs
______________________________________________________________Pin Description
PIN MAX520 DIP/SO 1 2 3 4 -- 6 5 7 8 -- -- -- -- 9 10 11 12 -- 13 14 15 16 SSOP 1 2 3 5 4, 7, 14, 17 8 6 9 10 -- -- -- -- 11 12 13 15 -- 16 18 19 20 DIP 1 2 3 4 -- 5 6 7 8 9 10 11 12 13 14 -- 15 16 17 18 19 20 MAX521 SO/SSOP 1 2 3 4 7, 9, 16, 20 5 6 8 10 11 12 13 14 15 17 -- 18 19 21 22 23 24 OUT1 OUT0 REF1 REF0 N.C. DGND AGND SCL SDA OUT4 OUT5 OUT6 OUT7 AD0 AD1 AD2 VDD REF4 REF3 REF2 OUT3 OUT2 DAC1 Voltage Output DAC0 Voltage Output Reference Voltage Input for DAC1 Reference Voltage Input for DAC0 No Connect--not internally connected Digital Ground Analog Ground Serial Clock Input Serial Data Input DAC4 Voltage Output DAC5 Voltage Output DAC6 Voltage Output DAC7 Voltage Output Address Input 0; sets IC's slave address Address Input 1; sets IC's slave address Address Input 2; sets IC's slave address Power Supply, +5V Reference Voltage Input for DACs 4, 5, 6, and 7 Reference Voltage Input for DAC3 Reference Voltage Input for DAC2 DAC3 Voltage Output DAC2 Voltage Output NAME FUNCTION
MAX520/MAX521
SDA tSU, DAT tLOW SCL tHD, STA tR START CONDITION tHIGH tF REPEATED START CONDITION STOP CONDITION START CONDITION tHD, DAT tSU, STA tHD, STA tSU, STO tBUF
Figure 1. 2-Wire Serial-Interface Timing Diagram
_______________________________________________________________________________________ 9
Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs MAX520/MAX521
_______________Detailed Description
Serial Interface
The MAX520/MAX521 use a simple 2-wire serial interface requiring only two I/O lines (2-wire bus) of a standard microprocessor (P) port. Figure 1 shows the timing diagram for signals on the 2-wire bus. Figure 2 shows the typical application of the MAX520/MAX521. The 2-wire bus can have several devices (in addition to the MAX520/MAX521) attached. The two bus lines (SDA and SCL) must be high when the bus is not in use. When in use, the port bits are toggled to generate the appropriate signals for SDA and SCL. External pull-up resistors are not required on these lines. The MAX520/MAX521 can be used in applications where pull-up resistors are required (such as in I2C systems) to maintain compatibility with the existing circuitry. The MAX520/MAX521 are receive-only devices and must be controlled by a bus master device. They operate at SCL rates up to 400kHz. A master device sends information to the devices by transmitting their address over the bus and then transmitting the desired information. Each transmission consists of a START condition, the MAX520/MAX521's programmable slave-address, one or more command-byte/output-byte pairs (or a command byte alone, if it is the last byte in the transmission), and finally, a STOP condition (Figure 3). The address byte and pairs of command and output bytes are transmitted between the START and STOP conditions. The SDA state is allowed to change only while SCL is low. SDA's state is sampled, and therefore must remain stable while SCL is high. The only exceptions to this are the START and STOP conditions. Data is transmitted in 8-bit bytes. Nine clock cycles are required to transfer the data bits to the MAX520/MAX521. Set SDA low during the 9th clock cycle as the MAX520/MAX521 pull SDA low during this time. RC (Figure 2) limits the current that flows during this time if SDA stays high for short periods of time.
C
SDA SCL REF0 REF1 REF2 REF3 OUT0 OUT2 OUT3 +1V +4V +5V
QUAD DAC
RC 1k
MAX520 OUT1
SCL SDA AD0 AD1 AD2
OFFSET ADJUSTMENT OFFSET ADJUSTMENT GAIN ADJUSTMENT GAIN ADJUSTMENT
+5V REF0 . . . OCTAL . DAC REF4 OUT0 MAX521 OUT1 OUT2 . SCL . . SDA AD0 OUT6 OUT7 AD1
BRIGHTNESS ADJUSTMENT CONTRAST ADJUSTMENT THRESHOLD ADJUSTMENTS +5V
+5V
MOTOR +12V
Figure 2. Typical Application Circuit
SLAVE ADDRESS BYTE SDA MSB SCL START CONDITION LSB ACK MSB
COMMAND BYTE
OUTPUT BYTE
LSB
ACK
MSB
LSB
ACK
STOP CONDITION
Figure 3. A Complete Serial Transmission
10 ______________________________________________________________________________________
Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs
START and STOP Conditions When the bus is not in use, both SCL and SDA must be high. A bus master signals the beginning of a transmission with a START condition by transitioning SDA from high to low while SCL is high (Figure 4). When the master has finished communicating with the slave, it issues a STOP condition by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission. Slave Address The MAX520/MAX521 each have a 7-bit-long slave address (Figure 5). The first four bits (MSBs) of the slave address have been factory programmed and are always 0101. In addition, the MAX521 has the next bit factory programmed to 0. The logic state of the address input pins (AD0, AD1, and AD2 of the MAX520; AD0 and AD1 of the MAX521) determine the least significant bits of the 7-bit slave address. These input pins may be connected to VDD or DGND, or they may be actively driven by TTL or CMOS logic levels. There are four possible slave addresses for the MAX521, and therefore a maximum of four such devices may be on the bus at one time. The MAX520 has eight possible slave addresses. The eighth bit (LSB) in the slave address byte should be low when writing to the MAX520/MAX521. The MAX520/MAX521 monitor the bus continuously, waiting for a START condition followed by its slave address. When a device recognizes its slave address, it is ready to accept data. Command Byte and Output Byte A command byte follows the slave address. Figure 6 shows the format for the command byte. A command byte is usually followed by an output byte unless it is the last byte in the transmission. If it is the last byte, all bits except PD and RST are ignored. If an output byte follows the command byte, A0-A2 of the command byte indicate the digital address of the DAC whose input data latch receives the digital output data. The data is transferred to the DAC's output latch during the STOP condition following the transmission. This allows all DACs to be updated and the new outputs to appear simultaneously (Figure 7). Setting the PD bit high powers down the MAX520/ MAX521 following a STOP condition (Figure 8a). If a command byte with PD set high is followed by an output byte, the addressed DAC's input latch will be updated and the data will be transferred to the DAC's output latch following the STOP condition (Figure 8b). If the transmission's last command byte has PD high, the voltage outputs will not reflect the newly entered data because the DAC will enter power-down mode when
MAX520/MAX521
SDA
SCL START CONDITION STOP CONDITION
Figure 4. All communications begin with a START condition and end with a STOP condition, both generated by a bus master.
SLAVE ADDRESS 0 SDA LSB SCL SLAVE ADDRESS BITS AD2, AD1, AND AD0 CORRESPOND TO THE LOGIC STATE OF THE ADDRESS INPUT PINS AD2, AD1, AND AD0. 1 0 1 0 or AD2 AD1 AD0 0 ACK
Figure 5. Address Byte
R2 SDA MSB SCL R2, R1, R0: RESERVED BITS. SET TO 0. RST: PD: RESET BIT, SET TO 1 TO RESET ALL DAC REGISTERS. POWER-DOWN BIT. SET TO 1 TO PLACE THE DEVICE IN THE 4A SHUTDOWN MODE. SET TO 0 TO RETURN TO THE NORMAL OPERATIONAL STATE. LSB R1 R0 RST PD A2 A1 A0 ACK
A2, A1, A0: ADDRESS BITS. DIGITAL ADDRESS FOR DAC0 TO DAC7. DETERMINES WHICH DAC'S INPUT LATCH RECEIVES THE 8 BITS OF DATA IN THE NEXT BYTE. A2 IS IGNORED BY THE MAX520. ACK: ACKNOWLEDGE BIT. THE MAX520/MAX521 PULL SDA LOW DURING THE 9TH CLOCK PULSE.
Figure 6. Command Byte
the STOP condition is detected. When in power-down, the MAX521's DAC outputs float, and the MAX520's unbuffered outputs look like a 16k resistor to AGND. In this mode, the supply current is a maximum of 20A. A command byte with the PD bit low returns the MAX520/MAX521 to normal operation following a STOP condition, and the voltage outputs reflect the current output-latch contents (Figures 9a and 9b). Because each subsequent command byte overwrites the previous PD bit, only the last command byte of a transmission affects the power-down state.
11
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Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs MAX520/MAX521
0 OR AD2 01 SDA ADDRESS BYTE START CONDITION ACK COMMAND BYTE (ADDRESSING DAC0) ACK OUTPUT BYTE (FULL SCALE) ACK COMMAND BYTE (ADDRESSING DAC1) ACK 0 1 AD1 AD0 0 0 0 0 0 0 0 0 000 1 1 1 1 1 1 1 1 0 00 0 0 00 0 1 0
(
1 1 1 00 ACK 0 0 0 0 01 00 ACK 1 0 0 0 0 COMMAND BYTE (ADDRESSING DAC2) DAC1 INPUT LATCH SET TO FULL SCALE
DAC0 INPUT LATCH SET TO FULL SCALE 0 0 0 0
)
1 SDA
1
1
1
1
OUTPUT BYTE (FULL SCALE)
(
Figure 7. Setting DAC Outputs
)
ACK OUTPUT BYTE STOP (HALF SCALE) CONDITION DAC2 INPUT LATCH SET TO HALF SCALE DAC OUTPUTS CHANGE HERE: DACS 0 AND 1 GO TO FULL SCALE, DAC 2 GOES TO HALF SCALE.
(
)
(
)
(a) 01 SDA 0 1
0 OR AD2 AD1 AD0 0 0 ACK
(PD) 00001 X X X COMMAND BYTE
0 ACK STOP CONDITION
ADDRESS BYTE START CONDITION (b) 01 SDA ADDRESS BYTE START CONDITION NOTE: X = DON'T CARE 0 1 0 OR AD2
(
DEVICE ENTERS POWER-DOWN STATE
)
0 ACK
AD1 AD0 0 0 0 ACK
0
0
0
(PD) 10
00
0 ACK
1
1
1
1
1
1
1
1
COMMAND BYTE (ADDRESSING DAC0)
OUTPUT BYTE (FULL SCALE)
(
STOP CONDITION DAC 0 INPUT LATCH SET TO FULL SCALE DEVICE ENTERS POWER-DOWN STATE. DAC 0 OUTPUT LATCH SET TO FULL SCALE.
)
(
)
Figure 8. Entering the Power-Down State
(a) 01 SDA 0 1
0 OR AD2 AD1 AD0 0
(PD) 000000 X X X ACK COMMAND BYTE
0 ACK STOP CONDITION
ADDRESS BYTE START CONDITION (b) 01 SDA ADDRESS BYTE START CONDITION NOTE: X = DON'T CARE 0 1 0 OR AD2 AD1 AD0 0
(
DEVICE RETURNS TO NORMAL OPERATION
)
0
00 ACK
0
0
0
(PD) 00
11
0 ACK
0
0
0
0
0
0
0
0
COMMAND BYTE (ADDRESSING DAC3)
ACK OUTPUT BYTE STOP (SET TO 0) DAC3 OUTPUT CONDITION LATCH SET TO 0 DEVICE RETURNS TO NORMAL OPERATION. DAC 3 SET TO 0.
(
) (
)
Figure 9. Returning to Normal Operation from Power-Down
12 ______________________________________________________________________________________
Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs MAX520/MAX521
(a) 01 SDA ADDRESS BYTE START CONDITION 0 OR AD2 01 SDA ADDRESS BYTE START CONDITION NOTE: X = DON'T CARE ACK 0 1 AD1 AD0 0 0 0 0 ACK 0 1 0 OR AD2 AD1 AD0 0 0 (RST) 00010 X COMMAND BYTE X X ACK STOP CONDITION 0
(
ALL INPUT LATCHES SET TO 0 0 X X X
)
(b)
(RST) 010
(
ALL OUTPUTS SET TO 0
)
0 ACK ADDITIONAL COMMAND BYTE/ OUTPUT BYTE PAIRS STOP CONDITION ALL DAC OUTPUTS SET TO 0 UNLESS CHANGED BY ADDITIONAL COMMAND BYTE/OUTPUT BYTE PAIRS
XXXXXXXX ACK "DUMMY" OUTPUT BYTE
COMMAND BYTE
(
ALL INPUT LATCHES SET TO 0
)
(
)
Figure 10. Resetting DAC Outputs
Setting the RST bit high clears all DAC input latches. The DAC outputs remain unchanged until a STOP condition is detected (Figure 10a). If a reset is issued, the following output byte is ignored. Subsequent pairs of command/output bytes overwrite the input latches (Figure 10b). All changes made during a transmission affect the MAX520/MAX521's outputs only when the transmission ends and a STOP has been recognized. The R0, R1, and R2 bits are reserved bits that must be set to zero.
C
SDA SCL SCL SDA
E PROM XICOR X24C04
2
I2C Compatibility
The MAX520/MAX521 are fully compatible with existing I2C systems. SCL and SDA are high-impedance inputs; SDA has an open drain which pulls the data line low during the 9th clock pulse. Figure 11 shows a typical I2C application.
SCL SDA AD0 AD1 AD2
QUAD DAC
MAX520
Additional START Conditions It is possible to interrupt a transmission to a MAX520/ MAX521 with a new START (repeated start) condition (perhaps addressing another device), which leaves the input latches with data that has not been transferred to the output latches (Figure 12). Only the currently addressed device will recognize a STOP condition and transfer data to its output latches. If the device is left with data in its input latches, the data can be transferred to the output latches the next time the device is addressed, as long as it receives at least one command byte and a STOP condition.
OCTAL DAC
+5V SCL SDA AD0 AD1
MAX521
Figure 11. Typical I2C Application Circuit
______________________________________________________________________________________ 13
Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs MAX520/MAX521
01 SDA START CONDITION ADDRESS BYTE (DEVICE 0) ACK COMMAND BYTE ADDRESSING DAC1 ACK OUTPUT BYTE (FULL SCALE) ACK ADDRESS BYTE (DEVICE 1) ACK 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 0 0 1 0 1 0 0 1 0 0
(
0 0 0 0 0 0 1 00 ACK 1 1 1 1 1 1 1 1 0 ACK COMMAND BYTE (ADDRESSING DAC2) OUTPUT BYTE (FULL SCALE)
DEVICE 0's DAC1 INPUT LATCH SET TO FULL SCALE
)
REPEATED START CONDITION
SDA STOP CONDITION ONLY DEVICE 1's DAC2 OUTPUT LATCH SET TO FULL SCALE. DEVICE 0's OUTPUT LATCHES UNCHANGED.
(
Figure 12. Repeated START Conditions
(a) 0 SDA ADDRESS BYTE START CONDITION 0 OR AD2 01 SDA ADDRESS BYTE START CONDITION ACK 0 1 AD1 AD0 0 0 0 0 ACK 10 1 0 OR AD2 AD1 AD0 0 0
DEVICE 1's DAC2 INPUT LATCH SET TO FULL SCALE
)(
)
(RST) (PD) 000110 INTERRUPTED COMMAND BYTE EARLY MAX520/MAX521's STATES STOP CONDITION REMAIN UNCHANGED
(
)
(b)
(PD) 0 RST 1 0
0
0
0
1
1
1
0
0
COMMAND BYTE (POWER DOWN)
ACK
INTERRUPTED OUTPUT BYTE EARLY STOP CONDITION
(
MAX520/MAX521 POWER DOWN; INPUT LATCHES UNCHANGED IF RST = 0, DAC OUTPUTS RESET IF RST = 1.
)
Figure 13. Early STOP Conditions
Early Stop Conditions The addressed device recognizes a STOP condition at any point in a transmission. If the STOP occurs during a command byte, all previous uninterrupted command and output byte pairs are accepted, the interrupted command byte is ignored, and the transmission ends (Figure 13a). If the STOP occurs during an output byte, all previous uninterrupted command and output byte pairs are accepted, the final command byte's PD and RST bits are accepted, the interrupted output byte is ignored, and the transmission ends (Figure 13b).
words into equivalent analog output voltages in proportion to the applied reference voltages. For both devices, DAC0-DAC3 each have separate reference inputs, while the MAX521's DAC4-DAC7 all share a common reference input. Figure 14 shows a simplified diagram of one DAC.
Analog Section
DAC Operation The MAX520 contains four matched voltage-output DACs, and the MAX521 contains eight. The DACs are inverted R-2R ladder networks that convert 8-bit digital
14
Reference Inputs The MAX520/MAX521 can be used for multiplying applications. The reference accepts a 0V to VDD voltage, both DC and AC signals. The voltage at each REF input sets the full-scale output voltage for its respective DAC(s). The reference voltage must be positive. The DAC's input impedance is code dependent, with the lowest value occurring when the input code is 55 hex or 0101 0101, and the maximum value occurring when the input code is 00 hex. Since the REF input resistance
______________________________________________________________________________________
Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs
MAX520 Unbuffered DAC Outputs
The unbuffered DAC outputs (OUT0-OUT3) connect directly to the internal 16k R-2R network. The outputs swing from 0V to VDD. The MAX520 has no output buffer amplifiers, giving it very low supply current. The output-offset voltage is lower without the output buffer, and the output can also slew and settle faster if capacitive loading is minimized. Resistive loading should be very light for highest accuracy. Any output loading generates some gain error, increasing full-scale error. The R-2R ladder's output resistance is 16k, so a 1A output current creates a 16mV error. Linearity is not affected because the ladder output resistance does not change with DAC code. Ladder-resistance changes with temperature are also very small. DACs are often used in trimming applications to replace hardware potentiometers. Figure 15a shows a typical application, which requires a buffered output so that a precise current can be injected into the summing node through precision resistor RT. For this application, the MAX520A features a precise 1% (TA = +25C, 2.5% over temperature) factory-trimmed output resistance. Because the MAX520A's output resistance is precisely trimmed, there is no need for an internal buffer or external precision resistor (Figure 15b). For applications where the output resistance value is not critical, use the MAX520B. All DACs exhibit output glitches during code transitions. An output filter is sometimes used to reduce these glitches in sensitive applications. The MAX520 simplifies output filtering because its internal resistive ladder network serves as the "R" in an RC filter. Simply connect a small capacitor from the DAC output to ground. See the Typical Operating Characteristics for oscilloscope photos of the worst-case 1LSB step change both without and with 25pF of capacitance on the MAX520's output.
MAX520/MAX521
OUT_ (MAX521) R R 2R D5 2R D6 R 2R D7 OUT_ (MAX520)
2R
2R D0
REF_ AGND SHOWN FOR ALL 1s ON DAC
Figure 14. DAC Simplified Circuit Diagram
(RIN) is code dependent, it must be driven by a circuit with low output impedance (no more than RIN / 2000) to maintain output linearity. The REF input capacitance is also code dependent, with the maximum value occurring at code FF hex (typically 30pF for the MAX520/ MAX521's REF0-REF3, and 120pF for the MAX521's REF4). The output voltage for any DAC can be represented by a digitally programmable voltage source as: VOUT = (N x VREF) / 256, where N is the numerical value of the DAC's binary input code. Table 1 shows the unipolar code.
Table 1. Unipolar Code Table
DAC CONTENTS 11111111 10000001 10000000 01111111 00000001 00000000 ANALOG OUTPUT 255 + VREF (------) 256 129 + VREF (------) 256 128 VREF + VREF (------) = ---- 256 2 127 + VREF (------) 256 1 + VREF (------) 256 0V
MAX521 Output Buffer Amplifiers
The MAX521 voltage outputs (OUT0-OUT7) are internally buffered precision unity-gain followers that slew up to 1V/s. The outputs can swing from 0V to VDD. With a 0V to 4V (or 4V to 0V) output transition, the amplifier outputs typically settle to 1/2LSB in 6s when loaded with 10k in parallel with 100pF. The buffer amplifiers are stable with any combination of resistive loads 2k and capacitive loads 300pF.
______________________________________________________________________________________
15
Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs MAX520/MAX521
RIN RF RIN RF
RT DAC (1%)
DAC
16k (1%)
MAX520A
Figure 15a. Typical Trimming Circuit
Figure 15b. MAX520A Trimming Circuit
__________Applications Information
Shutdown Mode
In shutdown mode, the MAX520/MAX521 reference inputs are disconnected from the R-2R ladder inputs, which saves power when the reference is not powered down. In addition, the MAX521's output buffers are disabled, greatly reducing the supply current. The MAX520's operating supply current does not change in shutdown mode. The Command Byte and Output Byte section describes how to enter and exit shutdown mode.
OUT2 OUT3 REF2 REF3
SYSTEM GND PIN1 OUT1 OUT0 REF1 REF0
Power-Supply Bypassing and Ground Management
Bypass VDD with a 0.1F capacitor, located as close to V DD and DGND as possible. The analog ground (AGND) and digital ground (DGND) pins should be connected in a "star" configuration to the highest quality ground available, which should be located as close to the MAX521 as possible. Careful PC board layout minimizes crosstalk among DAC outputs, reference inputs, and digital inputs. Figure 16 shows the suggested PC board layout to minimize crosstalk.
Figure 16. PC Board Layout for Minimizing Crosstalk (MAX521 bottom view, DIP package)
16
______________________________________________________________________________________
Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs
___________________________________________________Pin Configurations (continued)
TOP VIEW
OUT1 1 OUT0 2 REF1 3 N.C. 4 REF0 5 AGND 6 N.C. 7 DGND 8 SCL 9 SDA 10 20 OUT2 19 OUT3 18 REF2 17 N.C. OUT1 1 OUT0 2 REF1 3 REF0 4 DGND 5 AGND 6 SCL 7 SDA 8 OUT4 9 OUT5 10 20 OUT2 19 OUT3 18 REF2 OUT1 1 OUT0 2 REF1 3 REF0 4 DGND 5 AGND 6 N.C. 7 SCL 8 N.C. 9 SDA 10 OUT4 11 24 OUT2 23 OUT3 22 REF2 21 REF3
MAX520/MAX521
MAX520
MAX521
17 REF3 16 REF4 15 VDD 14 AD1 13 AD0 12 OUT7 11 OUT6
16 REF3 15 VDD 14 N.C. 13 AD2 12 AD1 11 AD0
MAX521
20 N.C. 19 REF4 18 VDD 17 AD1 16 N.C. 15 AD0 14 OUT7 13 OUT6
SSOP
DIP
OUT5 12
SO/SSOP
________________________________________________Functional Diagrams (continued)
SDA SCL
8 INPUT LATCH 0 1 INPUT LATCH 1 1 INPUT LATCH 2 1 INPUT LATCH 3 1 1 DECODE 8 8 8 8 INPUT LATCH 4 1 INPUT LATCH 5 1 8 INPUT LATCH 6 1 8 INPUT LATCH 7 OUTPUT LATCH 7 DAC7 OUTPUT LATCH 6 DAC6 OUTPUT LATCH 5 DAC5 OUTPUT LATCH 4 DAC4
REF2
OUTPUT LATCH 0
REF1 REF0 OUT0
DAC0
MAX521
8 8-BIT SHIFT REGISTER ADDRESS COMPARATOR START/STOP DETECTOR 8
OUT1
OUTPUT LATCH 1 DAC1
8
OUT2
OUTPUT LATCH 2 DAC2
OUT3
OUTPUT LATCH 3 DAC3
OUT4
OUT5
OUT6
OUT7
AD0
AD1
REF3 REF4
______________________________________________________________________________________
17
Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs MAX520/MAX521
__Ordering Information (continued)
PART
_________________Chip Topographies
MAX520
DGND AGND REF0 REF1 OUT0
TEMP. RANGE 0C to +70C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C -55C to +125C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C
PIN-PACKAGE 20 SSOP 20 SSOP Dice* Dice* 16 Plastic DIP 16 Plastic DIP 16 Wide SO 16 Wide SO 20 SSOP 20 SSOP 16 CERDIP 16 CERDIP 20 Plastic DIP 20 Plastic DIP 24 Wide SO 24 Wide SO 24 SSOP 24 SSOP Dice* 20 Plastic DIP 20 Plastic DIP 24 Wide SO 24 Wide SO 24 SSOP 24 SSOP 20 CERDIP
TUE (LSB) 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 2 1 2 2 1 2 1 2 1 2 2
REF0
MAX520ACAP MAX520BCAP MAX520AC/D MAX520BC/D MAX520AEPE MAX520BEPE MAX520AEWE MAX520BEWE MAX520AEAP MAX520BEAP MAX520AMJE MAX520BMJE MAX521ACPP MAX521BCPP MAX521ACWG MAX521BCWG MAX521ACAG MAX521BCAG MAX521BC/D MAX521AEPP MAX521BEPP MAX521AEWG MAX521BEWG MAX521AEAG MAX521BEAG MAX521BMJP
SCLK SDATA
OUT1
AD0 AD1 AD2
0.121" (3.073mm) OUT2
OUT3 REF2 V DD 0.098" (2.489mm) REF3
MAX521
REF1 OUT0 OUT1 OUT2 OUT3 REF2
REF3
DGND AGND
* Dice are specified at TA = +25C, DC parameters only. MAX520 "A" grade parts include a 1%-accurate, factory-trimmed output resistance.
0.212" (5.385mm)
AGND SCL SDA OUT4 OUT5 OUT6 OUT7 0.125" (3.175mm)
REF4 V DD AD1 AD0
TRANSISTOR COUNT: 4518 SUBSTRATE CONNECTED TO VDD
18 ______________________________________________________________________________________
Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs
________________________________________________________Package Information
E D A3 A A2 E1
DIM A A1 A2 A3 B B1 C D1 E E1 e eA eB L INCHES MAX MIN 0.200 - - 0.015 0.175 0.125 0.080 0.055 0.022 0.016 0.065 0.045 0.012 0.008 0.080 0.005 0.325 0.300 0.310 0.240 - 0.100 - 0.300 0.400 - 0.150 0.115 INCHES MIN MAX 0.348 0.390 0.735 0.765 0.745 0.765 0.885 0.915 1.015 1.045 1.14 1.265 MILLIMETERS MIN MAX - 5.08 0.38 - 3.18 4.45 1.40 2.03 0.41 0.56 1.14 1.65 0.20 0.30 0.13 2.03 7.62 8.26 6.10 7.87 2.54 - 7.62 - - 10.16 2.92 3.81 MILLIMETERS MIN MAX 8.84 9.91 18.67 19.43 18.92 19.43 22.48 23.24 25.78 26.54 28.96 32.13
21-0043A
MAX520/MAX521
L A1 e B D1
0 - 15 C B1 eA eB
Plastic DIP PLASTIC DUAL-IN-LINE PACKAGE (0.300 in.)
PKG. DIM PINS P P P P P N D D D D D D 8 14 16 18 20 24
DIM
D 0- 8 A e B
0.101mm 0.004in.
A1
C
L
A A1 B C E e H L
INCHES MAX MIN 0.104 0.093 0.012 0.004 0.019 0.014 0.013 0.009 0.299 0.291 0.050 0.419 0.394 0.050 0.016
MILLIMETERS MIN MAX 2.35 2.65 0.10 0.30 0.35 0.49 0.23 0.32 7.40 7.60 1.27 10.00 10.65 0.40 1.27
DIM PINS
E
H
Wide SO SMALL-OUTLINE PACKAGE (0.300 in.)
D D D D D
16 18 20 24 28
INCHES MIN MAX 0.398 0.413 0.447 0.463 0.496 0.512 0.598 0.614 0.697 0.713
MILLIMETERS MIN MAX 10.10 10.50 11.35 11.75 12.60 13.00 15.20 15.60 17.70 18.10
21-0042A
______________________________________________________________________________________
19
Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs MAX520/MAX521
___________________________________________Package Information (continued)
DIM A A1 B C D E e H L INCHES MILLIMETERS MIN MAX MIN MAX 0.068 0.078 1.73 1.99 0.002 0.008 0.05 0.21 0.010 0.015 0.25 0.38 0.004 0.008 0.09 0.20 SEE VARIATIONS 0.205 0.209 5.20 5.38 0.0256 BSC 0.65 BSC 0.301 0.311 7.65 7.90 0.025 0.037 0.63 0.95 0 8 0 8 INCHES MILLIMETERS MAX MIN MAX MIN 6.33 0.239 0.249 6.07 6.33 0.239 0.249 6.07 7.33 0.278 0.289 7.07 8.33 0.317 0.328 8.07 0.397 0.407 10.07 10.33
21-0056A
E
H
C
L
DIM PINS
e
A B D
A1
SSOP SHRINK SMALL-OUTLINE PACKAGE
D D D D D
14 16 20 24 28
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 (c) 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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